Content of DS and BX register is 2500H and 1000H, respectively. In microprocessor 8086, we have AX, BX, CX, DX and DS as registers. AX is called the accumulator. Each register is used to store values and perform operations. Microprocessors use assembly language to perform functions. MOV instructionRead more
Content of DS and BX register is 2500H and 1000H, respectively.
In microprocessor 8086, we have AX, BX, CX, DX and DS as registers. AX is called the accumulator. Each register is used to store values and perform operations.
Microprocessors use assembly language to perform functions.
MOV instruction is used to move contents from one register to other. The content where it is present is called the source register and where it is moved is called the destination register.
To move contents from DS to BX, use command:
MOV BX, [DS]
Here DS is the source register on the left and BX is the destination register on the right. Content will be moved from the register mentioned in the right to the register mentioned in the left. So content will be moved from DS to BX.
Segment Registers 1. 8086 addresses a segmented memory 2. Complete I MB memory is divided into 16 logical segments, each of 64 KB. 3. There are 4 segment registers: Code Segment (CS), Data Segment (DS), Extra Segment (ES) and Stack Segment (SS). 4. Segment Registers hold the offset address of the reRead more
Segment Registers
1. 8086 addresses a segmented memory
2. Complete I MB memory is divided into 16 logical segments,
each of 64 KB.
3. There are 4 segment registers: Code Segment (CS), Data
Segment (DS), Extra Segment (ES) and Stack Segment (SS).
4. Segment Registers hold the offset address of the respective
segments.
CS, code segment: Machine instructions exist at some offset into a code segment. The segment address of the code segment of the currently executing instruction is contained in CS.
DS, data segment: Variables and other data exist at some offset into a data segment. There may be many data segments, but the CPU may only use one at a time, by placing the segment address of that segment in register DS.
SS, stack segment: The stack is a very important component of the CPU used for temporary storage of data and addresses. Therefore, the stack has a segment address, which is contained in register SS.
ES, extra segment: The extra segment is exactly that: a spare segment that may be used for specifying a location in memory.
Q1.Forward engineering is not necessary if an existing software product is producing the correct output. Is the statement true or not. Justify with your answer. Answer: No, It's not true. As Forward Engineering is a method of creating or making an application with the help of the given requirements.Read more
Q1.Forward engineering is not necessary if an existing software product is producing the correct output. Is the statement true or not. Justify with your answer.
Answer:
No, It’s not true. As Forward Engineering is a method of creating or making an application with the help of the given requirements. Forward engineering is also known as Renovation and Reclamation. Forward engineering is a technique of creating high-level models or designs to make in complexities and low-level information. Therefore this kind of engineering has completely different principles in numerous package and information processes. Forward Engineering applies of all the software engineering process which contains SDLC to recreate associate existing application. It is near to full fill new needs of the users into re-engineering. Forward engineering deals with the conversion of business processes, services, and functions into applications. In this method business model is developed first. Then, a top-to-down approach is followed to urge the package from the model developed.
Q2.List and explain different types of testing done during the testing phase.
Answer:
Accessibility Testing
Accessibility testing is the practice of ensuring your mobile and web apps are working and usable for users without and with disabilities such as vision impairment, hearing disabilities, and other physical or cognitive conditions.
Acceptance Testing
Acceptance testing ensures that the end-user (customers) can achieve the goals set in the business requirements, which determines whether the software is acceptable for delivery or not. It is also known as user acceptance testing (UAT).
Black Box Testing
Black box testing involves testing against a system where the code and paths are invisible.
End to End Testing
End to end testing is a technique that tests the application’s workflow from beginning to end to make sure everything functions as expected.
Functional Testing
Functional testing checks an application, website, or system to ensure it’s doing exactly what it’s supposed to be doing.
Interactive Testing
Also known as manual testing, interactive testing enables testers to create and facilitate manual tests for those who do not use automation and collect results from external tests.
Integration Testing
Integration testing ensures that an entire, integrated system meets a set of requirements. It is performed in an integrated hardware and software environment to ensure that the entire system functions properly.
Features of Pentium Processor are as follows: Superscalar architecture Separate data and instruction caches Bus cycle pipelining Execution tracing 64-bit data bus Internal parity checking Dynamic branch prediction Dual processing support 256 lines between instruction cache and prefetch buffers; alloRead more
Features of Pentium Processor are as follows:
Superscalar architecture
Separate data and instruction caches
Bus cycle pipelining
Execution tracing
64-bit data bus
Internal parity checking
Dynamic branch prediction
Dual processing support
256 lines between instruction cache and prefetch buffers; allows 32 bytes to be transferred from cache to buffer
Data cache
8 KB dedicate data cache gives data to execution units
32 byte lines
Two parallel integer execution units
Allows the execution of two instructions to be executed simultaneously in a single processor clock
Floating point unit
It includes
Faster internal operations
Local advanced programmable interrupt controller
Speeds up upto 5 times for common operations including add, multiply and load, than 80486
Branch Prediction Logic
To reduce the time required for a branch caused by internal delays
When a branch instruction is encountered, microprocessor begins prefetch instruction at the branch address
Data Integrity and Error Detection
Has significant error detection and data integrity capability
Data parity checking is done on byte – byte basis
Address parity checking and internal parity checking features are added
Dual Integer Processor
Allows execution of two instructions per clock cycle
The other two (U pipe and V pipe) execute integer instructions
Parallel execution of several instructions – superscalar processor
(i)READY: This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1). (ii)INTR: The INTRRead more
(i)READY:
This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1).
(ii)INTR:
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
First completes the current instruction.
Activates INTA output and receives the interrupt type, say X.
Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack.
IP value is loaded from the contents of word location X × 4
CS is loaded from the contents of the next word location.
Interrupt flag and trap flag is reset to 0
(iii)NMI:
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
Completes the current instruction that is in progress.
Pushes the Flag register values on to the stack.
Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
IP is loaded from the contents of the word location 00008H.
CS is loaded from the contents of the next word location 0000AH.
If the content of DS and BX register is 2500H …
Content of DS and BX register is 2500H and 1000H, respectively. In microprocessor 8086, we have AX, BX, CX, DX and DS as registers. AX is called the accumulator. Each register is used to store values and perform operations. Microprocessors use assembly language to perform functions. MOV instructionRead more
Content of DS and BX register is 2500H and 1000H, respectively.
In microprocessor 8086, we have AX, BX, CX, DX and DS as registers. AX is called the accumulator. Each register is used to store values and perform operations.
Microprocessors use assembly language to perform functions.
MOV instruction is used to move contents from one register to other. The content where it is present is called the source register and where it is moved is called the destination register.
To move contents from DS to BX, use command:
MOV BX, [DS]
Here DS is the source register on the left and BX is the destination register on the right. Content will be moved from the register mentioned in the right to the register mentioned in the left. So content will be moved from DS to BX.
See lessGive the names of various registers carrying offset address of …
Segment Registers 1. 8086 addresses a segmented memory 2. Complete I MB memory is divided into 16 logical segments, each of 64 KB. 3. There are 4 segment registers: Code Segment (CS), Data Segment (DS), Extra Segment (ES) and Stack Segment (SS). 4. Segment Registers hold the offset address of the reRead more
Segment Registers
1. 8086 addresses a segmented memory
2. Complete I MB memory is divided into 16 logical segments,
each of 64 KB.
3. There are 4 segment registers: Code Segment (CS), Data
Segment (DS), Extra Segment (ES) and Stack Segment (SS).
4. Segment Registers hold the offset address of the respective
segments.
- CS, code segment: Machine instructions exist at some offset into a code segment. The segment address of the code segment of the currently executing instruction is contained in CS.
- DS, data segment: Variables and other data exist at some offset into a data segment. There may be many data segments, but the CPU may only use one at a time, by placing the segment address of that segment in register DS.
- SS, stack segment: The stack is a very important component of the CPU used for temporary storage of data and addresses. Therefore, the stack has a segment address, which is contained in register SS.
- ES, extra segment: The extra segment is exactly that: a spare segment that may be used for specifying a location in memory.
See lessFind The Minimum From Two 8 bit Numbers | Find The Largest of Two 8-bit numbers.
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See lessForward engineering is not necessary if an existing software product …
Q1.Forward engineering is not necessary if an existing software product is producing the correct output. Is the statement true or not. Justify with your answer. Answer: No, It's not true. As Forward Engineering is a method of creating or making an application with the help of the given requirements.Read more
Q1.Forward engineering is not necessary if an existing software product is producing the correct output. Is the statement true or not. Justify with your answer.
Answer:
No, It’s not true. As Forward Engineering is a method of creating or making an application with the help of the given requirements. Forward engineering is also known as Renovation and Reclamation. Forward engineering is a technique of creating high-level models or designs to make in complexities and low-level information. Therefore this kind of engineering has completely different principles in numerous package and information processes. Forward Engineering applies of all the software engineering process which contains SDLC to recreate associate existing application. It is near to full fill new needs of the users into re-engineering. Forward engineering deals with the conversion of business processes, services, and functions into applications. In this method business model is developed first. Then, a top-to-down approach is followed to urge the package from the model developed.
Q2.List and explain different types of testing done during the testing phase.
Answer:
Accessibility Testing
Accessibility testing is the practice of ensuring your mobile and web apps are working and usable for users without and with disabilities such as vision impairment, hearing disabilities, and other physical or cognitive conditions.
Acceptance Testing
Acceptance testing ensures that the end-user (customers) can achieve the goals set in the business requirements, which determines whether the software is acceptable for delivery or not. It is also known as user acceptance testing (UAT).
Black Box Testing
Black box testing involves testing against a system where the code and paths are invisible.
End to End Testing
End to end testing is a technique that tests the application’s workflow from beginning to end to make sure everything functions as expected.
Functional Testing
Functional testing checks an application, website, or system to ensure it’s doing exactly what it’s supposed to be doing.
Interactive Testing
Also known as manual testing, interactive testing enables testers to create and facilitate manual tests for those who do not use automation and collect results from external tests.
Integration Testing
Integration testing ensures that an entire, integrated system meets a set of requirements. It is performed in an integrated hardware and software environment to ensure that the entire system functions properly.
See lessEnlist the Technical Features of Pentium?
Features of Pentium Processor are as follows: Superscalar architecture Separate data and instruction caches Bus cycle pipelining Execution tracing 64-bit data bus Internal parity checking Dynamic branch prediction Dual processing support 256 lines between instruction cache and prefetch buffers; alloRead more
Features of Pentium Processor are as follows:
- Superscalar architecture
- Separate data and instruction caches
- Bus cycle pipelining
- Execution tracing
- 64-bit data bus
- Internal parity checking
- Dynamic branch prediction
- Dual processing support
- 256 lines between instruction cache and prefetch buffers; allows 32 bytes to be transferred from cache to buffer
- Data cache
- 8 KB dedicate data cache gives data to execution units
- 32 byte lines
- Two parallel integer execution units
- Allows the execution of two instructions to be executed simultaneously in a single processor clock
- Floating point unit
- It includes
- Faster internal operations
- Local advanced programmable interrupt controller
- Speeds up upto 5 times for common operations including add, multiply and load, than 80486
- Branch Prediction Logic
- To reduce the time required for a branch caused by internal delays
- When a branch instruction is encountered, microprocessor begins prefetch instruction at the branch address
- Data Integrity and Error Detection
- Has significant error detection and data integrity capability
- Data parity checking is done on byte – byte basis
- Address parity checking and internal parity checking features are added
- Dual Integer Processor
- Allows execution of two instructions per clock cycle
- The other two (U pipe and V pipe) execute integer instructions
- Parallel execution of several instructions – superscalar processor
See lessHow do READY, INTR and NMI Works in Microprocessor?
(i)READY: This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1). (ii)INTR: The INTRRead more
(i)READY:
This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1).
(ii)INTR:
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
(iii)NMI:
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
- Completes the current instruction that is in progress.
- Pushes the Flag register values on to the stack.
- Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
- IP is loaded from the contents of the word location 00008H.
- CS is loaded from the contents of the next word location 0000AH.
- Interrupt flag and trap flag are reset to 0.
See less