RISC processors best illustrate the difference between architecture and implementation. To what extent is this statement true (or not true)?

It is already stated that architecture and organization are orthogonal, i.e. they are independent. In principle, this statement is true. You can create an instruction set on paper and then implement it any way you want, via direct logic (called random logic) or via a structure such as microprogramming.

However, some design or organization techniques may be suited or unsuited to a particular architecture. CISC processors are characterized by both complicated instructions (i.e., multiple-part instructions or instructions with complex addressing modes), for example, the BFFFO (locate the occurrence of the first bit set to 1) can be regarded as a complex instruction and irregular instruction encodings.

Consequently, CISC instruction sets are well-suited to implementation/interpretation via microcode. The instruction lookup table simply translates a machine code value into the location of the appropriate microcode. It doesn’t matter how odd the instruction encoding is.

RISC processors with simple instructions are well suited to implementation by pipelining because of the regularity of a pipeline, i.e. all instructions are executed in approximately the same way.