(i) TEST:

• TEST pin is examined by the “WAIT” instruction. If the TEST pin is Low, execution continues. Otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

(ii) RQ/GT0 and RQ/GT1 :

• Request/Grant. These pins are used by local bus masters used to force the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.

(iii) QS0 and QS1 :

• Queue Status. These signals indicate the status of the internal 8086 instruction queue according to the table shown below

(iv) s0, s1, s2. :

• Status pins. These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for generating all the memory and I/O operation) access control signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.