(i)NMI :

It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these actions take place −

• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.

(ii) LOCK :

• It functions as the ¯LOCK output line. When this signal is active (i.e. low) the external bus master cannot take control of the system bus. It is activated when 8086 executes an instruction with the ¯LOCK prefix, and remains active till next instruction.
• LOCK Prefix: Normally a bus request is serviced after the current machine cycle and an interrupt request is serviced after the current instruction cycle. But if we write LOCK prefix before any instruction, then even if there is a bus request, the bus will be released only after the current instruction. Hence the bus is said to be locked during the instruction.

(iii) TEST :

• TEST pin is examined by the “WAIT” instruction. If the TEST pin is Low, execution continues. Otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

(iv) RESET :

• It is input pin to 8086. This is the reset input signal. The 8284 Clock generator provides it. It clears the Flag register and the Instruction Queue.
• It also clears the DS, SS, ES and IP registers and Sets the bits of CS register. Hence the reset vector address of 8086 is FFFFOH (as CS = FFFFH and IP = 0000H).